As a compression technique for a multilevel image, a conventional technique of segmenting a source image into blocks each constituted by a plurality of pixels, performing orthogonal transformation for each block, and quantizing the resultant data with a quantization threshold, thereby Huffman-coding the data is known. Such coding processing is used in the JPEG (Joint Photographic Experts Group) scheme. A coder/decoder implemented by forming this scheme into hardware is conventionally known.
In a coder implemented as hardware, attempts have been made to realize quantization processing at a high processing rate with a minimum circuit size. For example, orthogonal transformation factors converted in the zigzag scan sequence are processed for a plurality of factors at a time. The arrangement of a conventional coder will be described below.
A conventional coder performs orthogonal transformation, on a block basis, for an input source image segmented into a plurality of blocks by using an orthogonal transformer, and outputs orthogonal transformation factors. The output factors are rearranged in the zigzag scan sequence by a zigzag scan converter, and are output in twos to comparators. Corresponding quantization thresholds are also output in twos to the comparators. Each comparator compares the output factor with the corresponding quantization threshold and outputs comparison result information indicating whether the orthogonal transformat ion factor is smaller than the quantization threshold. This comparison result information is equivalent to information indicating whether the result obtained by quantizing the orthogonal transformation factor with the corresponding quantization threshold is 0.
A controller outputs control signals to selectors in accordance with output results from the comparators. More specifically, if at least one of quantization results on two orthogonal transformation factors is 0, the controller outputs control signals to the selectors to select one of the quantization results which is not 0 (significant factor) (if the two quantization results are 0, outputting control signals for selecting any quantization result exerts no influence on operation). If neither of the quantization results is 0, the controller outputs control signals to the selectors to alternately select the quantization results one by one in two cycles in accordance with the zigzag scan sequence. In addition, the controller outputs a format signal to the Huffman coder in accordance with the output results from the comparators. The format signal includes information indicating “a pair of 0 and significant factor” if one of the two orthogonal transformation factors is 0, “a pair of 0 and 0” if the two factors are 0, or “only one significant factor” if the two factors are significant factors (if the two factors are significant factors, since the factors are quantized one by one in two cycles, information indicating “only one significant factor” is consecutively output in two cycles), and information indicating, if the two factors are “a pair of 0 and significant factor”, which comes first in the zigzag scan sequence.
As described above, if an orthogonal transformation factor is 0, a result (i.e., 0) can be obtained without quantization processing. If, therefore, at least one of two orthogonal transformation factors is 0, control is performed to quantize the two orthogonal transformation factors substantially in one cycle. If, however, the two factors are significant as a result of comparison, since neither of the factors is 0, quantization processing is required. For this reason, a processing time of two cycles is required.
In a hardware-implemented decoder, attempts have been made to perform inverse quantization processing at a high processing rate with a minimum circuit size. For example, a technique of initializing a memory by performing inverse quantization processing for only significant factors of quantized orthogonal transformation factors and writing the resultant data in the memory has been proposed. The arrangement of a conventional decoder will be described below.
The conventional decoder decodes Huffman-coded data by using a Huffman decoder and outputs zero-run information indicating a quantized orthogonal transformation factor and the number of 0s preceding it. The output quantized orthogonal transformation factor is input to an inverse quantization unit to be inversely quantized by using a quantization threshold which corresponds to the quantized orthogonal transformation factor and is output from a quantization threshold table. The resultant data is output as an orthogonal transformation factor to a selector.
An address generator calculates a specific position in a block as an orthogonal transformation processing unit to which the output quantized orthogonal transformation factor corresponds on the basis of the output zero-run information, and outputs a write address in a block memory which corresponds to the position and a read address in the quantization threshold table. In addition, the address generator outputs an initialization target address for initialization of the block memory before quantization processing to the block memory for each unit block, and also outputs, to a controller, a signal indicating that initialization is being performed. The initialization processing is preprocessing in which 0s are written before processing for the unit block to limit orthogonal transformation factors to be written in the block memory to significant factors (factors that are not 0) in an actual processing stage, thereby omitting write processing for insignificant factors (factors which are 0). In this case, only addresses at which significant factors are written may be initialized. For this purpose, the addresses at which the significant factors were written must be stored. Write addresses for initialization are generated on the basis of the stored address information.
The quantization threshold table reads out quantization thresholds corresponding to quantized orthogonal transformation factors to be processed on the basis of outputs from the write address generator, and outputs them to the inverse quantization unit. The controller outputs a 0 value as initialization data and a sequence selection signal indicating whether to select the initialization data to the selector on the basis of a signal indicating that initialization is being performed, and also outputs a control signal for controlling write/read operation of the block memory to the read address generator. The control signal provides instructions to start read operation upon completion of write operation for a unit orthogonal transformation block, read two factors per cycle, terminate read operation when data corresponding to a unit orthogonal transformation block is read, start writing initialization data for initialization processing, and start write operation for the next processing target orthogonal transformation block upon completion of the initialization processing.
During a read interval, the read address generator generates addresses so as to sequentially read out in the zigzag scan sequence data corresponding to a unit orthogonal transformation processing block, which is written in the block memory, on the basis of the write/read control signal output from the controller, and outputs the addresses to the block memory.
The block memory operates in cycles of initialization of each orthogonal transformation processing unit block, write, and read in the zigzag scan sequence. The block memory operates to write an output from the selector at a write address and perform read operation according to a read address in accordance with the read/write control signal output from the controller. The read value is output to an inverse orthogonal transformer.
The inverse orthogonal transformer sequentially performs inverse orthogonal transformation for the orthogonal transformation factors output from the block memory in the zigzag scan sequence, and outputs the transformation results for each unit block.
With the above arrangement, write processing for the block memory requires clock cycles equal in number to the significant factors existing in a unit block. Since factors are read in twos, if the number of samples in a unit block is 64, 32 clock cycles are required. Initialization requires clock cycles equal in number to the significant factors existing in a unit block.
If, for example, the number of samples in a unit block is 64 and 20 significant factors exist in the unit block to be processed, the total number of clock cycles required for processing for the processing target block is the sum of write processing=20 cycles, read processing=32 cycles, and initialization processing=20 cycle, i.e., 72 clock cycles.
The number of clock cycles required to process a given unit orthogonal transformation block (8×8=64 samples) is minimized when the number of significant factors in the processing target block is 0. In this case, the total number of clock cycles is the sum of write processing=0 cycle, read processing=32 cycles, and initialization processing=0 cycle, i.e., 32 cycles. In contrast to this, the number of clock cycles required to process a given unit orthogonal transformation block is maximized when the number of significant factors in the processing target block is 64. In this case, the total number of clock cycles is the sum of write processing=64 cycles, read processing=32 cycles, and initialization processing 64 cycles, i.e., 160 cycles.
According to the arrangement of the conventional coder, at least one of quantization results on a pair of orthogonal transformation factors input to the comparing means is preferably 0 from the viewpoint of processing speed. For this purpose, the respective elements of quantized orthogonal transformation factors in an orthogonal transformation block are preferably input to the comparing means in such a manner that significant factors are proportionally dispersed as much as possible. If, however, these factors are input in the zigzag scan sequence, significant factors tend to concentrate on some part of a block. This makes it difficult to increase the coding speed.
According to the arrangement of the conventional decoder, if the compression ratio is high and the number of significant factors occupying each unit orthogonal transformation block is small, a high decoding speed can be obtained. However, since initialization processing is performed for each orthogonal transformation block, the processing speed decreases rapidly as the proportion of significant factors increases. As a result, the difference in time required for decoding between data with a high compression ratio and data with a low compression ratio increases.